Join Intel and build a better tomorrow.
Manufacturing Development and Customer Engagement (MDCE) is responsible for the ramping of production of all Intel silicon using some of the world's most advanced manufacturing processes in fabs in Arizona, Ireland, Israel, Oregon and future greenfield sites. Intel recently created MDCE to strengthen its yield operation and enable fast-paced yield ramp-up in early HVM phases for each technology in collaboration with Technology Development team and fab managers.
This job requisition is for a Defect Metrology Development engineering role in MDCE, reporting to Defect Metro Engineering Development manager.
A successful candidate will work with other members in defect metro team, other teams in the MDCE org, fab module, yield, integration, and TD team members to achieve yield ramp-up and defect reduction in early production stage, supporting internal and external customers.
Collaborate with Technology Development team and Process Integration team to import and setup new technology to production fabs across the globe.
Identify critical yield limiting defect steps and work with Defect Control team to set production line inspection strategy to protect yield and quality at maximum productivity and lowest cost.
Candidate should possess the following behavioural skills:
Problem-solving and project/program management experience with strong self-initiative and self-learning capabilities.
Demonstrated interpersonal skills to perform at leadership role including influencing, engaging, and motivating.
Proven track record of working across organization through matrix structures to accomplish strategic objectives with conflicting priorities.
Must demonstrate strong communication skills.
Flexibility to work with global teams on a global time differential as needed.
Establish and implement workflows and procedures for continuous improvement programs to ensure quality and prevent yield excursions in line and sort processes
Analyze structured and unstructured data to deliver insights into process health and enable decision on improvement activities
Assess quality and reliability risks for manufacturing materials and process changes, ensuring adherence to Intel's standards.
Minimum Qualifications:
Bachelor's or Master's degree in science and engineering major, with at least 10+ years of industry experience or PhD degree in science and engineering with at least 8 years industry experience.
Strong understanding on defect mechanism and yield impact in semiconductor high-volume production and proven quantified track record of driving down D0.
4+ years of experience in advanced node semiconductor industry in Defect engineering.
Experience in Statistics and Machine Learning preferred.
Experience in working with Process Integration, Design and OPC teams to identify layout-sensitive defect weak points and address systematic defect issues.
Knowledge of module tool impacts to defects, inline parametric and yield through PM life while understanding upstream and downstream impacts to other tools
Experience in FinFET technology development or high-volume manufacturing with hands-on knowledge of FinFET technology process flow to analyse systematic defect sources and set mitigation actions.
Working knowledge in module processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology. Skills to develop improvement projects at module level to improve process for reduced defectivity and improved yield.
Candidate must possess at least one of the following:
Preferred Qualifications:
Bachelor's or Advanced degree (Master's or Ph.D.) in Electrical Engineering, Physics, Chemistry or Materials Science major is preferred, with at least 10+ years of experience.
Experience in project/program management and/or Task Force Team lead.
Experience in customer and stakeholder management.
Must demonstrate solid communication skills.
Ability to work with multi-functional, multi-cultural teams.
Demonstrated interpersonal skills including influencing, engaging, and motivating.
Problem-solving technique with strong self-initiative and self-learning capabilities.
Ability to leverage big data analysis to identify process design weaknesses and/or manufacturing weaknesses to propose corrective, data-based solutions.
Ability to extracts insights from structured and unstructured data by quickly synthesizing large volumes of data and applying statistics and machine learning.
Experience in new semiconductor technology development.
Experience in serving external Foundry customers through technical interactions.
Experience in FinFET and GAA (Gate-All-Around) technology architecture.
Experienced Hire
Shift 1 (Ireland)
Ireland, Leixlip
Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers - from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
