Find Principal engineer, design verification engineering Jobs in Sandyford County Dublin

ASIC Digital Design, Staff Engineer
Synopsys —Dublin, County Dublin
- Master's degree
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Principal Engineer, Design Verification Engineering
Analog Devices —Dublin, County Dublin
- Full-time
- Master's degree
- Scripting
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Principal Engineer - Product Group Engineering Modernisation & AI Adoption
U.S. Bank National Association —DUBLIN 18, County Dublin
- €117,980–€138,800 a year
- Full-time
- Azure
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Lab Testing Technician (GMP Medical Devices)
PM Group —Dublin, County Dublin
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EXL Service —Dublin, County Dublin
- Full-time
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Head of Professional Services
PFH Technology Group —Dublin, County Dublin
- Full-time
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Quick apply
Regional Medical Devices Integration Lead / Clinical Engineer NRS15556
Health Service Executive —Dublin, County Dublin
- Part-time
- In-person
9d
Principal Digital Design Engineer (f/m/div)
Infineon Technologies AG —Dublin, County Dublin
- English
- Bachelor's degree
- Communication skills
Principal Enabling Works Engineer & Project Manager - Major Transportation Infrastructure Delivery, Roads & Public Transportation
AECOM —Dublin, County Dublin
- Full-time
- Hybrid work
- Engineering
- No degree
- Civil Engineering
Principal Environmental Consultant (EIA Projects)
AECOM —Dublin, County Dublin
- Full-time
- Hybrid work
- Master's degree
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- Leadership
Principal Engineer Digital Design (f/m/div)
Infineon Technologies AG —Dublin, County Dublin
- Engineering
- English
- Bachelor's degree
Director of Engineering
CarTrawler —Dublin, County Dublin
- Hybrid work
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Senior Analog Design Manager (m/f/div)
Infineon Technologies AG —Dublin, County Dublin
- English
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Principal Silicon Validation Engineer
Qorvo —DUBLIN 8, County Dublin
- Engineering
- Data analysis skills
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Principal Engineer, Component Engineering
Analog Devices —Glasnevin, County Dublin
- Full-time
- Doctoral degree
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Staff Quality Engineer II
BD —Dublin, County Dublin
- €75,900–€115,725 a year
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- Analysis skills
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Engineering Manager - Commerce Hub
Fiserv —Dublin, County Dublin
- Full-time
- Java
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Quality Engineer - Fuze Services - Fixed Term Contract
Fuze Health —Northern Cross, County Dublin
- €60,000–€68,000 a year
- Full-time
- ERP systems
- Master's degree
- Analysis skills
- Annual leave
- Employee assistance program
6d
Principal DevOps Engineer - Decision Management Platform
Mastercard —Dublin, County Dublin
- Full-time
- DevOps
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- AWS
Principal Maritime Engineer
Mott MacDonald —Dublin, County Dublin
- Full-time
- Hybrid work
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- Business
- Communication skills
- Annual leave
- Life insurance
3d

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ASIC Digital Design, Staff Engineer

Synopsys -
Dublin, County Dublin

Apply Now

Job details

Qualifications

Master's degree
Analysis skills
Bachelor's degree
Computer Engineering
AI
Communication skills
Debugging

Full job description

We Are:

At Synopsys, we drive the innovations that shape how we live and connect. Our technology is central to the Era of Pervasive Intelligence — from self-driving cars to learning machines — and we lead in chip design, verification, and IP integration that power high-performance silicon and software.

Within our HPC Controller IP organization, the mid-end team is the bridge between RTL design and physical implementation. We build the flows, automation, and quality checks that synthesize, verify, package, and release complex soft IP at scale — and we hand physical-design teams inputs that are clean, constrained, and implementation-ready.

You Are:

A motivated mid-end engineer with a solid grasp of ASIC design and verification flows, and genuine enthusiasm for automation, flow robustness, and using AI to raise engineering productivity, debug speed, and quality of results. You partner naturally with RTL designers to understand design intent, turn their outputs into physical-design-ready inputs, and collaborate across verification, DFT, physical design, methodology, and tooling teams. You communicate clearly, take ownership, and let data guide your decisions.

What You’ll Be Doing:

Develop, run, and support mid-end flows spanning synthesis, DFT, static checking (SpyGlass), formal equivalence, power analysis, and related quality gates.
Convert RTL outputs into clean, constrained, implementation-ready inputs for physical design.
Build and maintainTcl-based automation, dashboards, and project infrastructure — and apply AI to accelerate the work (e.g., triaging flow logs, summarizingQoRtrends, drafting and refactoring scripts).
Debug flow failures end to end:analyzereports, isolate root cause, and drive issues to closure with design, verification, DFT, and implementation teams.
Improve documentation, handoff criteria, and reusable collateral so execution stays consistent across IP programs.

The Impact You Will Have:

Higher-quality RTL-to-physical-designhandoffs and lower implementation risk.
Faster, more scalable execution through stronger automation and AI-enabled analysis.
Synthesis, DFT, static, formal, and power issues caught earlier in the cycle.
Tighter collaboration across the RTL-to-implementation chain.
Robust, implementation-ready soft IP shipped with clear constraints, checks, and release collateral.

What You’ll Need(Core):

Working knowledge of ASIC design, verification, and mid-end development flows, typically gained through 5+ years of relevant experience or equivalent project work.
Hands-on synthesis experience, with the ability toanalyzeand resolve synthesis issues.
StrongTclscripting skills and a practical, automation-first mindset.
Familiarity with at least two of: DFT concepts, static checking (SpyGlassor equivalent), formal equivalence (e.g., Formality), or power analysis — and willingness to grow across the rest.
Ability to use AI tools effectively to accelerate debugging, summarize results, and improve scripts and flows.
Strong analytical, problem-solving, communication, and documentation skills.
BS/MS in Electrical/Computer Engineering or equivalent experience.

Nice to have :

Experience across the full mid-end set: DFT,SpyGlass, Formality, and power analysis.
IP development methodologies, IP packaging, or reusable IP delivery / release collateral.
Hands-on with Synopsys tools such as Fusion Compiler and VCSpyGlass.

Who You Are:

Proactive, curious, and adaptable.
Collaborative and ethical.
Flow-oriented, AI-aware, and quality focused.
Resilient and resultsoriented.

The Team You’ll Be A Part Of:

You’ll work with a high-impact High-Performance-Compute team focused on delivering complex IP to the marketplace. You will collaborate across RTL design, verification, DFT, physical design, methodology, and project infrastructure teams to improve mid-end readiness and enable predictable downstream implementation.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about salary and benefits during the hiring process.

Apply Now

Refine Your Search

principal engineer, design verification engineering jobs in sandyford county dublin

ASIC Digital Design, Staff Engineer

Principal Engineer, Design Verification Engineering

Principal Engineer - Product Group Engineering Modernisation & AI Adoption

Lab Testing Technician (GMP Medical Devices)

Head of Architecture and Engineering Operations

Head of Professional Services

Regional Medical Devices Integration Lead / Clinical Engineer NRS15556

Principal Digital Design Engineer (f/m/div)

Principal Enabling Works Engineer & Project Manager - Major Transportation Infrastructure Delivery, Roads & Public Transportation

Principal Environmental Consultant (EIA Projects)

Principal Engineer Digital Design (f/m/div)

Director of Engineering

Senior Analog Design Manager (m/f/div)

Principal Silicon Validation Engineer

Principal Engineer, Component Engineering

Staff Quality Engineer II

Engineering Manager - Commerce Hub

Quality Engineer - Fuze Services - Fixed Term Contract

Principal DevOps Engineer - Decision Management Platform

Principal Maritime Engineer

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