Find Machine learning engineer Jobs in Sandyford County Dublin

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EDA flow and Logic Synthesis Engineer (Senior Engineer)

Synopsys -
Dublin, County Dublin

Apply Now

Job details

Qualifications

Master's degree
Bachelor's degree
Computer Engineering
Scripting
AI
Communication skills
Debugging

Full job description

Date posted 06/29/2026

Category Engineering Hire Type Employee Job ID 17918 Remote Eligible No Date Posted 06/29/2026

We Are:

At Synopsys, we drive the innovations that shape how we live and connect. Our technology is central to the Era of Pervasive Intelligence — from self-driving cars to learning machines — and we lead in chip design, verification, and IP integration that power high-performance silicon and software.

Within our HPC Controller IP organization, the mid-end team is the bridge between RTL design and physical implementation. We build the flows, automation, and quality checks that synthesize, verify, package, and release complex soft IP at scale — and we hand physical-design teams inputs that are clean, constrained, and implementation-ready.

You Are:

A motivated mid-end engineer with a solid grasp of ASIC design and verification flows, and genuine enthusiasm for automation, flow robustness, and using AI to raise engineering productivity, debug speed, and quality of results. You partner naturally with RTL designers to understand design intent, turn their outputs into physical-design-ready inputs, and collaborate across verification, DFT, physical design, methodology, and tooling teams. You communicate clearly, take ownership, and let data guide your decisions.

What You’ll Be Doing:

Develop, run, and support mid-end flows spanning synthesis, DFT, static checking (SpyGlass), formal equivalence, power analysis, and related quality gates.
Convert RTL outputs into clean, constrained, implementation-ready inputs for physical design.
AI to accelerate the work (e.g., triaging flow logs, summarizing QoR trends, drafting and refactoring scripts).
Debug flow failures end to end: analyze reports, isolate root cause, and drive issues to closure with design, verification, DFT, and implementation teams.
Improve documentation, handoff criteria, and reusable collateral so execution stays consistent across IP programs.

The Impact You Will Have:

Higher-quality RTL-to-physical-design handoffs and lower implementation risk.
Faster, more scalable execution through stronger automation and AI-enabled analysis.
Synthesis, DFT, static, formal, and power issues caught earlier in the cycle.
Tighter collaboration across the RTL-to-implementation chain.
Robust, implementation-ready soft IP shipped with clear constraints, checks, and release collateral.

What You’ll Need(Core):

Working knowledge of ASIC design, verification, and mid-end development flows, typically gained through 2+ years of relevant experience or equivalent project work.
Hands-on synthesis experience, with the ability to analyze and resolve synthesis issues.
Good Tcl scripting skills and a practical, automation-first mindset.
Familiarity with some of the following: DFT concepts, static checking (SpyGlass or equivalent), formal equivalence (e.g., Formality), or power analysis — and willingness to grow across the rest.
Ability to use AI tools effectively to accelerate debugging, summarize results, and improve scripts and flows.
Good analytical, problem-solving, communication, and documentation skills.
BS/MS in Electrical/Computer Engineering or equivalent experience.

Nice to have :

Some experience across the full mid-end set: DFT, SpyGlass, Formality, and power analysis.
IP development methodologies, IP packaging, or reusable IP delivery / release collateral.
Hands-on with Synopsys tools such as Fusion Compiler and VC SpyGlass.

Who You Are:

Proactive, curious, and adaptable.
Collaborative and ethical.
Flow-oriented, AI-aware, and quality focused.
Resilient and results oriented.

The Team You’ll Be A Part Of:

You’ll work with a high-impact High-Performance-Compute team focused on delivering complex IP to the marketplace. You will collaborate across RTL design, verification, DFT, physical design, methodology, and project infrastructure teams to improve mid-end readiness and enable predictable downstream implementation.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about salary and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Apply Now

Refine Your Search

machine learning engineer jobs in sandyford county dublin

EDA flow and Logic Synthesis Engineer (Senior Engineer)

Senior AI Security Engineer (R-19324)

Director of Software Engineering

Senior Software Engineer, Java

VP of Quantum Software Engineering

Okta on Okta Identity Architect

Senior Engineering Manager, Embedded Product Security

Lead Databricks Architect

Growth Manager - EdTech (French fluent)

Senior Engineering Manager, Customer Agent

Senior Data Scientist

ASIC Design/Verification, Architect

Marketing Manager - EdTech (French fluent )

ASIC Digital Verification Architect

Senior Social Media Manager - French Fluent

Enterprise Growth Account Executive, DACH

ASIC Digital Design, Architect

Enterprise Account Executive, Nordics

Senior AI Large Language Model (LLM) Architect

Data Engineer

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Category Engineering Hire Type Employee Job ID 17918 Remote Eligible No Date Posted 06/29/2026

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