We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent years building digital IP that has to meet ISO 26262 ASIL D, not just pass functional verification. You know the difference between a controller that works in simulation and one that survives FMEDA, DFMEA, and real-world automotive stress, and you have debugged enough corner cases to know where those gaps usually hide. You think in RTL, but you also think in safety mechanisms, fault injections, and what it takes to qualify hardware for a car that cannot fail.
You are comfortable leading RTL development for a PCIe or DDR controller while also mentoring engineers through lint cleanup, CDC convergence, and synthesis QoR.
What You'll Be Doing
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Design and own RTL for automotive digital IP blocks, with a focus on PCIe, DDR, or UCIe controllers that meet ISO 26262 functional safety requirements
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Lead RTL coding, lint and CDC analysis, synthesis optimization, and debug across complex IP subsystems
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Work closely with verification teams to define Verification IP scope, identify feature coverage gaps, and ensure controllers are fully validated before tapeout
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Drive safety qualification activities including DFMEA, FMEDA, and DFA for IP targeting ASIL D
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Mentor and guide engineering teams through design flows, coding standards, and best practices for synthesizable Verilog and System Verilog
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Apply and evaluate AI-driven design tools and methodologies to improve design quality and automation
The Impact You Will Have
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Enable Synopsys automotive IP to meet the most stringent functional safety standards, supporting customers building ASIL D systems
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Deliver production-quality RTL for high-speed interface IP that powers next-generation automotive SoCs
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Reduce design cycle time and improve quality by introducing AI-driven design flows and automation
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Close critical gaps between design intent and verification coverage, preventing late-stage bugs and costly respins
What You'll Need
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Bachelor's degree with 8+ years or Master's degree with 6+ years of relevant experience in Automotive SoCs or Digital IPs
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Proven IP-level experience with protocols like PCIe, DDR, or UCIe, with PCIe experience strongly preferred
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Demonstrated ability to work as an individual contributor while mentoring and leading engineering teams through RTL coding, lint/CDC analysis, synthesis, and debug
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Experience qualifying embedded hardware systems to ISO 26262 ASIL levels up to ASIL D, and working with DFMEA, FMEDA, and DFA
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In-depth experience writing synthesizable Verilog/System Verilog for ASIC design and simulation tools
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Strong command of ASIC design flows, including lint, CDC, synthesis, Static Timing Analysis, and formal verification
Who You Are
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You can explain a complex safety tradeoff to a systems architect in two sentences without losing the technical nuance
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You push back when a verification plan misses a critical fault scenario or a design spec leaves ambiguity that will cost time later
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You are organized enough to manage RTL delivery, safety documentation, and team mentorship in parallel without dropping threads
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You treat design automation as part of the job, not an afterthought, and you write scripts that others on the team actually use
The Team You'll Be Part Of
Your recruiter will share more about the team structure and mission during the interview process.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
