Find Machine learning engineer Jobs in Carrickmines, D

ASIC Digital Design, Sr Engineer
Synopsys —Dublin, County Dublin
- Master's degree
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AstraZeneca —Dublin, County Dublin
- Computer Science
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Core Engineer, Director
Integral Ad Science, Inc. —Dublin, County Dublin
- €162,400–€278,400 a year
- Full-time
- Doctoral degree
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7d
Director, Engineering
Integral Ad Science, Inc. —Dublin, County Dublin
- €162,400–€278,400 a year
- Full-time
- Doctoral degree
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- Annual leave
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5d
Senior Solutions Engineer,Auth0
Okta —Dublin, County Dublin
- €104,000–€143,000 a year
- Sales
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- Presentation skills
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Data Engineering Lead
Wibit Consulting & Services (WibitCS) —Dublin, County Dublin
- Full-time
- Azure
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11d
Sr.Quality Assurance Engineer (German/French Speaking), Alexa Global Quality Team
Amazon Development Centre Ireland Limited - D94 —Dublin, County Dublin
- Full-time
- Java
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Senior Data Engineer
The Irish Times —Dublin, County Dublin
- Full-time
- Hybrid work
- Azure
- Doctoral degree
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Engineering Manager
Learnosity —Dublin, County Dublin
- Full-time
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- Computer Science
- Master's degree
- AWS
- Annual leave
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12d
Director, Finance Transformation
KAYAK —DUBLIN 2, County Dublin
- Full-time
- Remote
- Computer Science
- Engineering
- ERP systems
- Annual leave
- Employee assistance program
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14d
Engineering Manager, Security
Dolby —Dublin, County Dublin
- Computer Science
- Research
- Master's degree
SMB Account Executive - Benelux
Okta —Dublin, County Dublin
- €88,000–€120,000 a year
- Bachelor's degree
- In-person
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- Annual leave
Sr. Lead Security Engineer - Google Cloud Platform
JPMorganChase —DUBLIN 2, County Dublin
- Full-time
- Computer Science
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ASIC Digital Design, Principal Engineer
Synopsys —Dublin, County Dublin
- Computer Science
- Engineering
- Bachelor's degree
Sr Applied Scientist
2K —Dublin, County Dublin
- Doctoral degree
- Master's degree
- SQL
Quick apply
Senior Software Engineer - Commerce Hub
Fiserv —Dublin, County Dublin
- Full-time
- Java
- Master's degree
- AWS
7d
Newly/Nearly qualified actuary
AXA —DUBLIN 1, County Dublin
- SQL
- Communication skills
- Python
7d

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ASIC Digital Design, Sr Engineer

Synopsys -
Dublin, County Dublin

Apply Now

Job details

Qualifications

Master's degree
Bachelor's degree
Computer Engineering
Scripting
AI
Communication skills
Debugging

Full job description

We Are:

At Synopsys, we drive the innovations that shape how we live and connect. Our technology is central to the Era of Pervasive Intelligence — from self-driving cars to learning machines — and we lead in chip design, verification, and IP integration that power high-performance silicon and software.

Within our HPC Controller IP organization, the mid-end team is the bridge between RTL design and physical implementation. We build the flows, automation, and quality checks that synthesize, verify, package, and release complex soft IP at scale — and we hand physical-design teams inputs that are clean, constrained, and implementation-ready.

You Are:

A motivated mid-end engineer with a solid grasp of ASIC design and verification flows, and genuine enthusiasm for automation, flow robustness, and using AI to raise engineering productivity, debug speed, and quality of results. You partner naturally with RTL designers to understand design intent, turn their outputs into physical-design-ready inputs, and collaborate across verification, DFT, physical design, methodology, and tooling teams. You communicate clearly, take ownership, and let data guide your decisions.

What You’ll Be Doing:

Develop, run, and support mid-end flows spanning synthesis, DFT, static checking (SpyGlass), formal equivalence, power analysis, and related quality gates.
Convert RTL outputs into clean, constrained, implementation-ready inputs for physical design.
Build and maintain Tcl-based automation, dashboards, and project infrastructure — and apply AI to accelerate the work (e.g., triaging flow logs, summarizing QoR trends, drafting and refactoring scripts).
Debug flow failures end to end: analyze reports, isolate root cause, and drive issues to closure with design, verification, DFT, and implementation teams.
Improve documentation, handoff criteria, and reusable collateral so execution stays consistent across IP programs.

The Impact You Will Have:

Higher-quality RTL-to-physical-design handoffs and lower implementation risk.
Faster, more scalable execution through stronger automation and AI-enabled analysis.
Synthesis, DFT, static, formal, and power issues caught earlier in the cycle.
Tighter collaboration across the RTL-to-implementation chain.
Robust, implementation-ready soft IP shipped with clear constraints, checks, and release collateral.

What You’ll Need(Core):

Working knowledge of ASIC design, verification, and mid-end development flows, typically gained through 2+ years of relevant experience or equivalent project work.
Hands-on synthesis experience, with the ability to analyze and resolve synthesis issues.
Good Tcl scripting skills and a practical, automation-first mindset.
Familiarity with some of the following: DFT concepts, static checking (SpyGlass or equivalent), formal equivalence (e.g., Formality), or power analysis — and willingness to grow across the rest.
Ability to use AI tools effectively to accelerate debugging, summarize results, and improve scripts and flows.
Good analytical, problem-solving, communication, and documentation skills.
BS/MS in Electrical/Computer Engineering or equivalent experience.

Nice to have :

Some experience across the full mid-end set: DFT, SpyGlass, Formality, and power analysis.
IP development methodologies, IP packaging, or reusable IP delivery / release collateral.
Hands-on with Synopsys tools such as Fusion Compiler and VC SpyGlass.

Who You Are:

Proactive, curious, and adaptable.
Collaborative and ethical.
Flow-oriented, AI-aware, and quality focused.
Resilient and results oriented.

The Team You’ll Be A Part Of:

You’ll work with a high-impact High-Performance-Compute team focused on delivering complex IP to the marketplace. You will collaborate across RTL design, verification, DFT, physical design, methodology, and project infrastructure teams to improve mid-end readiness and enable predictable downstream implementation.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about salary and benefits during the hiring process.

Apply Now

Refine Your Search

machine learning engineer jobs in carrickmines, d

ASIC Digital Design, Sr Engineer

Build the Future of AI with Us – Dublin (Hybrid)

Development Manager

Senior ML Science Manager

Senior Data Engineer — Lab Data Pipelines & Data Mesh (12 month FTC)

Core Engineer, Director

Director, Engineering

Senior Solutions Engineer,Auth0

Data Engineering Lead

Sr.Quality Assurance Engineer (German/French Speaking), Alexa Global Quality Team

Senior Data Engineer

Engineering Manager

Director, Finance Transformation

Engineering Manager, Security

SMB Account Executive - Benelux

Sr. Lead Security Engineer - Google Cloud Platform

ASIC Digital Design, Principal Engineer

Sr Applied Scientist

Senior Software Engineer - Commerce Hub

Newly/Nearly qualified actuary

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