Find Junior software engineer Jobs in Greystones, Ww

ASIC Digital Design, Principal Engineer
Synopsys —Dublin, County Dublin
- Leadership
- Communication skills
8d
Senior Engineering Manager, Fin AI Agent
Intercom —Dublin, County Dublin
- Hybrid work
- AI
- Annual leave
- Work from home
Principal Civil Engineer
AtkinsRéalis —Dublin, County Dublin
- Full-time
- Hybrid work
- Communication skills
VacancyTitle: Senior Hydraulic Modeller - Wastewater
Nicholas O'Dwyer —Dublin, County Dublin
- Full-time
- Hybrid work
- Project management
- Bachelor's degree
- Business
- Annual leave
- Employee assistance program
Senior HV Design Engineer
Designer Group —Dublin, County Dublin
- AutoCAD
- Master's degree
- In-person
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Structural Senior/Associate - Dublin
EirEng Consulting Engineers —Dublin, County Dublin
- Full-time
- Annual leave
- Work from home
Senior Quantity Surveyor - Water
Turner & Townsend —Dublin, County Dublin
- Full-time
- Hybrid work
- Annual leave
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5d

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Senior Engineering Manager, Fin AI Agent
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Flexible paid time off policy. The engineering decisions made in the next 12 months will determine who wins. Communication. You can explain to leadership why a…
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Lead and mentor a team of 6-10 engineers, guiding them through the entire software development lifecycle—from research and prototyping to deployment and…
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ASIC Digital Design, Principal Engineer

Synopsys -
Dublin, County Dublin

Apply Now

Job details

8 days ago

Qualifications

Leadership
Communication skills

Full job description

We Are

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are

An experienced and visionary Principal ASIC Digital Design, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in design methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of protocols such as DDR, PCIe/CXL, UCIe, AMBA and its applications. You can define and executing a new architecture for protocols such as UAL (Universal Accelerator Link). You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects.

What You’ll Be Doing

Defining and developing ASIC RTL design and verification at both chip and block levels.
Creating and executing design plans for complex digital designs, particularly focusing on DDR, PCIe,CXL,UAL, UCIe IO protocols.
Collaborating with cross-functional teams to ensure seamless integration and functionality of designs.
Utilizing advanced design and verification methodologies and tools to achieve high-quality results.
Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement.
Communicating with internal and external stakeholders to align on project goals and deliverables.

The Impact You Will Have

Enhancing the reliability and performance of Synopsys’ digital design processes.
Driving innovations in DDR, PCIe, UAL, UCIe technology, contributing to the development of cutting-edge semiconductor solutions.
Improving time-to-market for high-performance silicon chips through efficient methodologies.
Building and nurturing a highly skilled development team, elevating overall project quality.
Influencing strategic decisions that shape the future of Synopsys’ capabilities.
Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements.

What You’ll Need

Extensive experience in ASIC RTL design.
In-depth knowledge of DDR, PCIe, UAL, UCIe and similar IO protocols and their applications.
Proficiency in advanced digital design tools and methodologies.
Strong problem-solving skills and the ability to work independently.
Excellent communication skills for effective collaboration with diverse teams.

Who You Are

A visionary leader with a strategic mindset.
A mentor who fosters talent and encourages innovation.
A proactive problem solver who thrives in complex environments.
An effective communicator with the ability to convey technical concepts to a broad audience.
A team player who values collaboration and diversity.

The Team You’ll Be A Part Of

You will join a dynamic and innovative team focused on advancing Synopsys' design technologies. Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry. Specifically, according to a match profile, you will be a key technical contributor to the architecture and execution of one of DDR/PCIe/UAL/UCIe digital core protocols.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Apply Now

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junior software engineer jobs in greystones, ww

ASIC Digital Design, Principal Engineer

Senior Engineering Manager, Fin AI Agent

Principal Civil Engineer

VacancyTitle: Senior Hydraulic Modeller - Wastewater

Senior HV Design Engineer

Structural Senior/Associate - Dublin

Senior Quantity Surveyor - Water

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