Find Digital verification Jobs in Temple Bar County Dublin

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Synopsys —Dublin, County Dublin
- Master's degree
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WSP —Dublin, County Dublin
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Hitachi —Dublin, County Dublin
- Full-time
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Project Manager
Hitachi Rail —Dublin, County Dublin
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- Bachelor's degree
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2d
ASIC Digital Design, Sr Staff Engineer
Synopsys —Dublin, County Dublin
- Master's degree
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Strategic Account Manager – Rail
Murphy Geospatial —Dublin, County Dublin
- Full-time
- Hybrid work
- Construction experience
- Communication skills
- Gym membership
Quick apply
ASIC Digital Design, Architect
Synopsys —Dublin, County Dublin
- Leadership
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Technical Architect / Architect (Advanced Technology)
DPS Group —Dublin, County Dublin
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Associate Director - Roads, Public Transport, & Greenways
AECOM —Dublin, County Dublin
- Full-time
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Project Engineering Manager
ALSTOM —Dublin, County Dublin
- €100,000 a year
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Fusion Account Executive - Expansion Dutch/German speaker
Autodesk —Dublin, County Dublin
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- Full-time
- English
Technical Sales Manager, Grid Automation
Hitachi —Dublin, County Dublin
- Full-time
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Senior Service Engineer
Hitachi —Dublin, County Dublin
- Full-time
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Senior Account Executive Expansion (German Speaker)
Autodesk —Dublin, County Dublin
- €74,250–€108,900 a year
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Senior NPU SDK Software Engineer
Innatera Nanosystems —Dublin, County Dublin
- Full-time
- Hybrid work
- Computer Science
- Master's degree
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Quick apply
Technical Sales Manager, Grid Automation
Hitachi Rail —Dublin, County Dublin
- Full-time
- CRM software
- Sales
- Microsoft Office
Principal Electrical Engineer
AtkinsRéalis —Dublin, County Dublin
- Full-time
- Hybrid work
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ASIC Digital Design, Sr Engineer

Synopsys -
Dublin, County Dublin

Apply Now

Job details

Qualifications

Master's degree
Bachelor's degree
Computer Engineering
Scripting
AI
Communication skills
Debugging

Full job description

We Are:

At Synopsys, we drive the innovations that shape how we live and connect. Our technology is central to the Era of Pervasive Intelligence — from self-driving cars to learning machines — and we lead in chip design, verification, and IP integration that power high-performance silicon and software.

Within our HPC Controller IP organization, the mid-end team is the bridge between RTL design and physical implementation. We build the flows, automation, and quality checks that synthesize, verify, package, and release complex soft IP at scale — and we hand physical-design teams inputs that are clean, constrained, and implementation-ready.

You Are:

A motivated mid-end engineer with a solid grasp of ASIC design and verification flows, and genuine enthusiasm for automation, flow robustness, and using AI to raise engineering productivity, debug speed, and quality of results. You partner naturally with RTL designers to understand design intent, turn their outputs into physical-design-ready inputs, and collaborate across verification, DFT, physical design, methodology, and tooling teams. You communicate clearly, take ownership, and let data guide your decisions.

What You’ll Be Doing:

Develop, run, and support mid-end flows spanning synthesis, DFT, static checking (SpyGlass), formal equivalence, power analysis, and related quality gates.
Convert RTL outputs into clean, constrained, implementation-ready inputs for physical design.
Build and maintain Tcl-based automation, dashboards, and project infrastructure — and apply AI to accelerate the work (e.g., triaging flow logs, summarizing QoR trends, drafting and refactoring scripts).
Debug flow failures end to end: analyze reports, isolate root cause, and drive issues to closure with design, verification, DFT, and implementation teams.
Improve documentation, handoff criteria, and reusable collateral so execution stays consistent across IP programs.

The Impact You Will Have:

Higher-quality RTL-to-physical-design handoffs and lower implementation risk.
Faster, more scalable execution through stronger automation and AI-enabled analysis.
Synthesis, DFT, static, formal, and power issues caught earlier in the cycle.
Tighter collaboration across the RTL-to-implementation chain.
Robust, implementation-ready soft IP shipped with clear constraints, checks, and release collateral.

What You’ll Need(Core):

Working knowledge of ASIC design, verification, and mid-end development flows, typically gained through 2+ years of relevant experience or equivalent project work.
Hands-on synthesis experience, with the ability to analyze and resolve synthesis issues.
Good Tcl scripting skills and a practical, automation-first mindset.
Familiarity with some of the following: DFT concepts, static checking (SpyGlass or equivalent), formal equivalence (e.g., Formality), or power analysis — and willingness to grow across the rest.
Ability to use AI tools effectively to accelerate debugging, summarize results, and improve scripts and flows.
Good analytical, problem-solving, communication, and documentation skills.
BS/MS in Electrical/Computer Engineering or equivalent experience.

Nice to have :

Some experience across the full mid-end set: DFT, SpyGlass, Formality, and power analysis.
IP development methodologies, IP packaging, or reusable IP delivery / release collateral.
Hands-on with Synopsys tools such as Fusion Compiler and VC SpyGlass.

Who You Are:

Proactive, curious, and adaptable.
Collaborative and ethical.
Flow-oriented, AI-aware, and quality focused.
Resilient and results oriented.

The Team You’ll Be A Part Of:

You’ll work with a high-impact High-Performance-Compute team focused on delivering complex IP to the marketplace. You will collaborate across RTL design, verification, DFT, physical design, methodology, and project infrastructure teams to improve mid-end readiness and enable predictable downstream implementation.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about salary and benefits during the hiring process.

Apply Now

Refine Your Search

digital verification jobs in temple bar county dublin

ASIC Digital Design, Sr Engineer

Design Coordinator, Rail – Dublin

Tendering Specialist

Secondary Project Engineer

Principal Commercial Analyst

Site Supervisor

Project Manager

ASIC Digital Design, Sr Staff Engineer

Strategic Account Manager – Rail

ASIC Digital Design, Architect

Technical Architect / Architect (Advanced Technology)

Associate Director - Roads, Public Transport, & Greenways

Project Engineering Manager

Fusion Account Executive - Expansion Dutch/German speaker

Technical Sales Manager, Grid Automation

Senior Service Engineer

Senior Account Executive Expansion (German Speaker)

Senior NPU SDK Software Engineer

Technical Sales Manager, Grid Automation

Principal Electrical Engineer

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