Find Lead machine learning engineer Jobs in Dublin County Dublin

ASIC Design/Verification, Architect
Synopsys —Dublin, County Dublin
- Analysis skills
- Communication skills
ASIC Digital Verification Architect
Synopsys —Dublin, County Dublin
- Leadership
- Communication skills
Data Engineer
Grouper —Dublin, County Dublin
- Full-time
- Hybrid work
- Azure
- Computer Science
- SQL
Quick apply
Senior Data Scientist
Verve —Dublin, County Dublin
- Doctoral degree
- Master's degree
- SQL
Senior Manager, Solutions Engineering, Okta
Okta —Dublin, County Dublin
- €140,000–€190,000 a year
- Sales
- Annual leave
3h
Senior Manager, Solutions Engineering, Okta
Okta —Dublin, County Dublin
- €140,000–€190,000 a year
- Sales
Quick apply
4h

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ASIC Digital Verification Architect
Synopsys —Dublin, County Dublin
Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects. Knowledge of DDR Protocol a plus.
ASIC Design/Verification, Architect
Synopsys —Dublin, County Dublin
Familiarity with wider digital ASIC and IP development flow, including RTL design through synthesis. Strong understanding of digital design and verification…

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ASIC Design/Verification, Architect

Synopsys -
Dublin, County Dublin

Apply Now

Job details

Qualifications

Analysis skills
SystemVerilog
Communication skills

Full job description

Date posted 06/22/2026

Category Engineering Hire Type Employee Job ID 16711 Remote Eligible No Date Posted 06/22/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

An experienced and highly skilled ASIC Digital Verification Engineer with a passion for ensuring the highest quality in digital design. You have a deep understanding of verification methodologies and are proficient in using advanced verification tools and techniques. Your expertise allows you to work independently, taking on complex challenges and delivering innovative solutions. You are detail-oriented, with a strong analytical mindset, and can communicate effectively with various stakeholders. Your ability to mentor and lead junior engineers is a testament to your extensive experience in the field. You thrive in a collaborative environment and are committed to continuous learning and improvement.

What You’ll Be Doing:

Designing, implementing and optimizing verification environments to ensure the correctness of Interface IP protocols.
Creating, executing and tracking against detailed test plans to verify complex ASIC designs.
Developing and maintaining verification IP and testbenches using System Verilog and UVM.
Collaborating with design and architecture teams identifying fix bugs.
Performing functional coverage analysis and driving coverage closure.
Mentoring and guiding junior verification engineers in best practices and methodologies.

The Impact You Will Have:

Ensuring the delivery of high-quality, reliable ASIC designs that meet customer specifications.
Enhancing the robustness and efficiency of our verification processes and methodologies.
Contributing to the successful launch of Interface IP products, impacting various industries.
Driving innovation and excellence within the verification team.
Improving the overall performance and functionality of Synopsys' IP offerings.
Fostering a culture of continuous improvement and technical excellence.

What You’ll Need:

Extensive experience in ASIC digital verification, specifically with Interface IP protocols, such as PCIe, CXL, DDR, Ethernet, AMBA (CHI, AXI, AHB, APB).
Proficiency in System Verilog, SVA and UVM methodologies.
Strong understanding of digital design and verification concepts.
Familiarity with wider digital ASIC and IP development flow, including RTL design through synthesis.
Experience with simulation tools such as VCS, Model Sim, or similar.
Strong analytical and problem-solving skills, with the ability to tackle complex and unique design challenges.
Excellent communication skills, with the ability to effectively collaborate with cross-functional teams and stakeholders.

Who You Are:

Detail-oriented with a strong analytical mindset.
Excellent communicator, able to convey complex technical concepts clearly.
Collaborative team player who thrives in a dynamic environment.
Proactive and self-motivated, with a commitment to continuous learning.
Mentor and leader, capable of guiding and developing junior engineers.

The Team You’ll Be A Part Of:

You will be part of a highly skilled and motivated verification team focused on delivering cutting-edge Interface IP solutions. The team is dedicated to maintaining the highest standards of quality and performance, working collaboratively to tackle complex verification challenges. You will have the opportunity to work alongside industry experts and contribute to the development of next-generation technologies.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Apply Now

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lead machine learning engineer jobs in dublin county dublin

ASIC Design/Verification, Architect

ASIC Digital Verification Architect

Data Engineer

Senior Data Scientist

Senior Manager, Solutions Engineering, Okta

Senior Manager, Solutions Engineering, Okta

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Category Engineering Hire Type Employee Job ID 16711 Remote Eligible No Date Posted 06/22/2026

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